28 Mar '17, 7pm

#LeadingEdge…

One simple metric is gate pitch (gate width plus spacing between transistor gates) multiplied by minimum metal pitch (interconnect line width plus spacing between lines), but this doesn’t incorporate logic cell design, which affects the true transistor density. Another metric, gate pitch multiplied by logic cell height, is a step in the right direction with regard to this deficiency. But neither of these takes into account some second order design rules. And both are not a true measure of actual achieved density because they make no attempt to account for the different types of logic cells in a designer’s library. Furthermore, these metrics quantify density relative to the previous generation. What is really needed is an absolute measure of transistors in a given area (per mm2 ). At the other extreme, simply taking the total transistor count of a chip and dividing by its a...

Full article: https://newsroom.intel.com/editorials/lets-clear-up-node-...

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eetimes.com 29 Mar '17, 1am

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via @eetimes

eetimes.com 29 Mar '17, 4am

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newsroom.intel.com 28 Mar '17, 9pm

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tolonews.com 28 Mar '17, 9am

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